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| STR73xF ARM7TDMITM 32-bit MCU with Flash, 3x CAN, 4 UARTs, 20 timers, ADC, 12 comm. interfaces Core - ARM7TDMI 32-bit RISC CPU - 32 MIPS @ 36 MHz Memories - Up to 256 Kbytes FLASH program memory (10,000 cycles endurance, data retention 20 years @ 85 C) - 16 Kbytes RAM Clock, reset and supply management - 4.5 - 5.5V application supply and I/Os - Embedded 1.8V regulator for core supply - Embedded oscillator running from external 4-8MHz crystal or ceramic resonator - Up to 36 MHz CPU freq. with internal PLL - Internal RC oscillator 32kHz or 2MHz software configurable for fast startup and backup clock - Realtime Clock for clock-calendar function - Wakeup Timer driven by internal RC for wakeup from STOP mode - 5 power saving modes: SLOW, WFI, LPWFI, STOP and HALT modes Nested interrupt controller - Fast interrupt handling with multiple vectors - 64 maskable IRQs with 64 vectors and 16 priority levels - 2 maskable FIQ sources - 16 ext. interrupts, up to 32 wake-up lines TQFP100 14 x 14 TQFP144 20 x 20 LFBGA144 10 x 10 x 1.7 DMA - 4 DMA controllers with 4 channels each Timers - 16-bit watchdog timer (WDG) - 6/10 16-bit timers (TIM) each with: 2 input captures, 2 output compares, PWM and pulse counter modes - 6 16-bit PWM modules (PWM) - 3 16-bit timebase timers with 8-bit prescalers 12 communications interfaces - 2 I2C interfaces - 4 UART asynchronous serial interfaces - 3 BSPI synchronous serial interfaces - Up to 3 CAN interfaces (2.0B Active) 10-bit A/D converter - 12/16 channels - Conversion time: min. 3 s, range: 0 to 5V Development tools support - JTAG interface Up to 112 I/O ports - 72/112 multifunctional bidirectional I/Os Table 1. Device summary Features FLASH memory - bytes RAM - bytes Peripheral Functions CAN Peripherals Operating Voltage Operating Temperature Packages T=TQFP144 20 x 20 H=LFBGA144 10 x10 STR730FZx 128K 256K 16K STR735FZx 128K STR731FVx 64K 128K 256K 16K 64K STR736FVx 128K 256K 256K 10 TIM Timers, 112 I/Os, 32 Wake-Up lines, 16 ADC channels 3 0 6 TIM Timers, 72 I/Os, 18 Wake-Up lines, 12 ADC channels 3 4.5 to 5.5V 0 -40 to +85C/-40 to +105C T=TQFP100 14x14 September 2006 Rev 6 1/53 www.st.com 53 Contents STR73xF Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 2.2.2 2.2.3 STR730F/STR735F (TQFP144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STR730F/STR735F (LFBGA144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STR731F/STR736F (TQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.1 4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2/53 STR73xF Contents 6 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1 6.2 Low Power Wait For Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL free running mode at high temperature . . . . . . . . . . . . . . . . . . . . . . 51 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3/53 Introduction STR73xF 1 Introduction This datasheet provides the STR73x Ordering Information, Mechanical and Electrical Device Characteristics. For complete information on the STR73xF Microcontroller memory, registers and peripherals. please refer to the STR73x Reference Manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference Manual. 1.1 Overview ARM core with embedded Flash & RAM STR73xF family combines the high performance ARM7TDMITM CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. The STR73xF family has an embedded ARM core and is therefore compatible with all ARM tools and software. Extensive tools support STMicroelectronics' 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST's ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available. For more information, please refer to ST MCU site http://www.st.com/mcu Figure 1 shows the general block diagram of the device family. Package Choice: Reduced Pin-Count TQFP100 or Feature-Rich 144-pin TQFP or LFBGA The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions have the full set of all features. The 100-pin version has fewer timers, I/Os and ADC channels. Refer to the Device Summary on Page 1 for a comparison of the I/Os available on each package. The family includes versions with and without CAN. 4/53 STR73xF High Speed Flash Memory Introduction The Flash program memory is organized in 32-bit wide memory cells which can be used for storing both code and data constants. It is accessed by CPU with zero wait states @ 36 MHz. The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming. The Flash memory endurance is 10K write/erase cycles and the data retention is 20 years @ 85 C. IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: Sector Write Protection Flash Debug Protection (locks JTAG access) Flexible Power Management To minimize power consumption, you can program the STR73xF to switch to SLOW, WFI LPWFI, STOP or HALT modes depending on the current system activity in the application. Flexible Clock Control Two clock sources are used to drive the microcontroller, a main clock driven by an external crystal or ceramic resonator and an internal backup RC oscillator that operates at 2MHz or 32 kHz. The embedded PLL can be configured to generate an internal system clock of up to 36 MHz. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. Voltage Regulators The STR73xF requires an external 4.5 to 5.5V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply needed by the core and peripherals. The main VR is switched off and the Low Power VR switched on when the application puts the STR73xF in Low Power Wait for Interrupt (LPWFI) mode. Low Voltage Detectors The voltage regulator and Flash modules each have an embedded LVD that monitors the internal 1.8V supply. If the voltage drops below a certain threshold, the LVD will reset the STR73xF. Note: An external power-on reset must be provided ensure the microcontroller starts-up correctly. 5/53 Introduction STR73xF 1.2 On-Chip Peripherals CAN Interfaces The three CAN modules are compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. These are not available in the STR735 and STR736. DMA 4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to peripheral, peripheral to memory and memory to peripheral transfers. The DMA requests are connected to TIM timers, BSPI0, BSPI1, BSPI2 and ADC. One of the streams can be configured to be triggered by a software request, independently from any peripheral activity. 16-bit Timers (TIM) Each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. This provides a total of 16 independent PWMs (12 in 100-pin devices) when added with the PWM modules (see next paragraph). PWM Modules (PWM) The six 16-bit PWM modules have independently programmable periods and duty-cycles, with 5+3 bit prescaler factor. Timebase Timers (TB) The three 16-bit Timebase Timers with 8-bit prescaler for general purpose time triggering operations. Realtime Clock (RTC) The RTC provides a set of continuously running counters driven by separate clock signal derived from the main oscillator. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR73xF is in LPWFI mode the RTC keeps running, powered by the low power voltage regulator. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 625K baud. Buffered Serial Peripheral Interfaces (BSPI) Each of the three BSPIs allow full duplex, synchronous communications with external devices, master or slave communication at up 6 Mb/s (@36 MHz System Clock). I2C Interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. A/D Converter The 10-bit Analog to Digital Converter, converts up to 16 channels in single-shot or continuous conversion modes (12 channels in 100-pin devices). The minimum conversion time is 3us. 6/53 STR73xF Watchdog Introduction The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O Ports Up to 112 I/O ports (72 in 100-pin devices) are programmable as general purpose input/output or Alternate Function. External Interrupts and Wake-Up Lines 16 external interrupts lines are available for application use. In addition, up to 32 external Wakeup lines (18 in 100-pin devices) can be used as general purpose interrupts or to wakeup the application from STOP mode. 7/53 Block Diagram STR73xF 2 Block Diagram Figure 1. RSTIN STR730F/STR735F block diagram PRCCU/PLL ARM7TDMI CPU ARM7 NATIVE BUS FLASH Program Memory 64/128/256K RAM 16K APB BRIDGE 0 APB BRIDGE 1 M0 M1 TEST JTDI JTCK JTMS JTRST JTDO V18 VDD VSS VDDA VSSA JTAG POWER SUPPLY VREG AHB BRIDGE AHB BUS DMA0-3 CLOCK MGT (CMU) XTAL1 XTAL2 OSC RTC WATCHDOG I2C0-1 WAKEUP/INT (WIU) UART0, 1, 2, 3 APB BUS APB BUS 4 AF 32 AF 8 AF INTERRUPT CTL (EIC) 16 AF 12 AF 12 AF 6 AF 6 AF 122 ports A/D CONVERTER (ADC) TIMER (TIM) 2-4 BSPI 0-2 CAN 0-2* PWM 0-5 GPIO PORTS 0-6 TIMEBASE TIMER (TB) 0-2 WAKEUP TIMER (WUT) TIMER (TIM) 0-1 TIMER (TIM) 5-9 8 AF 20 AF *CAN peripherals not available on STR735F. AF: alternate function on I/O port pin 8/53 STR73xF Figure 2. RSTIN Block Diagram STR731F/STR736 block diagram PRCCU/PLL ARM7TDMI CPU ARM7 NATIVE BUS FLASH Program Memory 64/128/256K RAM 16K APB BRIDGE 0 APB BRIDGE 1 M0 M1 TEST JTDI JTCK JTMS JTRST JTDO V18 VDD VSS VDDA VSSA JTAG POWER SUPPLY VREG AHB BRIDGE AHB BUS DMA0-3 CLOCK MGT (CMU) XTAL1 XTAL2 OSC RTC WATCHDOG I2C0-1 WAKEUP/INT (WIU) UART0, 1, 2, 3 APB BUS APB BUS 4 AF 18 AF 8 AF INTERRUPT CTL (EIC) 12 AF 12 AF 12 AF 6 AF 6 AF 72 ports A/D CONVERTER (ADC) TIMER (TIM) 2-4 BSPI 0-2 CAN 0-2* PWM 0-5 GPIO PORTS 0-6 TIMEBASE TIMER (TB) 0-2 WAKEUP TIMER (WUT) TIMER (TIM) 0-1 TIMER (TIM) 5 8 AF 4 AF *CAN peripherals not available on STR736F. AF: alternate function on I/O port pin 9/53 Block Diagram STR73xF 2.1 Related Documentation Available from www.arm.com: ARM7TDMI Technical Reference Manual Available from http://www.st.com: STR73x Reference Manual STR7 Flash Programming Reference Manual STR73x Software Library User Manual For a list of related application notes refer to http://www.st.com. 10/53 STR73xF Block Diagram 2.2 2.2.1 Pin description STR730F/STR735F (TQFP144) Figure 3. STR730F/STR735F pin configuration (top view) P6.15 / WUP9 P6.14 / SS0 P6.13 / SCK0 / WUP11 P6.12 / MOSI0 P6.11 / MISO0 P6.10 / WUP8 P6.9 / TDO0 P6.8 / RDI0 / WUP10 P6.7 / WUP7 P6.6 / WUP6 P6.5 / WUP5 P6.4 / TDO3 / WUP4 P6.3 / WUP3 P6.2 / RDI3 / WUP2 P6.1 / WUP1 P6.0 / WUP0 VDD VSS V18 P5.15 / INT13 P5.14 / INT12 P5.13 / INT11 P5.12 / INT10 P5.11 / TDO2 / INT9 P5.10 / RDI2 / INT8 P5.9 / INT7 P5.8 / INT6 P5.7 / MISO2 P5.6 / MOSI2 P5.5 / SCK2 / WUP23 P5.4 / SS2 P5.3 / OCMPB9 P5.2 / OCMPA9 P5.1 / MISO1 P5.0 / MOSI1 P4.15 / SCK1 / WUP22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 OCMPB2 / P0.0 OCMPA2 / P0.1 ICAPA2 / P0.2 ICAPB2 / P0.3 VSS VDD OCMPA5 / P0.4 OCMPB5 / P0.5 ICAPA5 / P0.6 ICAPB5 / P0.7 OCMPA6 / P0.8 OCMPB6 / P0.9 OCMPA7 / P0.10 OCMPB7 / P0.11 VDD VSS ICAPA3 / P0.12 ICAPB3 / P0.13 OCMPB3 / P0.14 OCMPA3 / P0.15 OCMPA4 / P1.0 OCMPB4 / P1.1 ICAPB4 / P1.2 ICAPA4 / P1.3 VSS VDD P1.4 P1.5 OCMPB1 / P1.6 OCMPA1 / P1.7 INT0 / OCMPA0 / P1.8 INT1 / OCMPB0 / P1.9 ICAPB0 / WUP28 / P1.10 ICAPA0 / WUP29 / P1.11 ICAPA1 / WUP30 / P1.12 ICAPB1 / WUP31 / P1.13 STR730F/STR735F P4.14 / SS1 P4.13 / ICAPB9 P4.12 / ICAPA9 / WUP21 P4.11 / OCMPB8 P4.10 / ICAPA6 / WUP20 P4.9 / ICAPB6 P4.8 / OCMPA8 P4.7 / SDA1 P4.6 / SCL1 / WUP19 P4.5 / CAN2RX / WUP18 P4.4 / CAN2TX P4.3 / ICAPB8 / WUP27 P4.2 / ICAPA8 / WUP26 P4.1 / ICAPB7 / WUP25 P4.0 / ICAPA7 / WUP24 VDD VSS JTDO JTCK JTMS JTDI JTRST VSS VDD P3.15 / AIN15 / INT5 P3.14 / AIN14 / INT4 P3.13 / AIN13 / INT3 P3.12 / AIN12 / INT2 P3.11 / AIN11 P3.10 / AIN10 P3.9 / AIN9 P3.8 / AIN8 VDDA VSSA P3.7 / AIN7 P3.6 / AIN6 Note 1: CAN alternate functions not available on STR735F. WUP12 / CAN0RX / P1.14 CAN0TX / P1.15 PWM0 / P2.0 WUP13 / CAN1RX / P2.1 CAN1TX / P2.2 PWM1 / P2.3 PWM2 / P2.4 PWM3 / P2.5 PWM4 / P2.6 PWM5 / P2.7 M0 RSTIN M1 VDD VSS XTAL1 XTAL2 VSS TDO1 / P2.8 WUP14 / RDI1 / P2.9 WUP16 / P2.10 WUP17 / P2.11 INT14 / P2.12 INT15 / P2.13 WUP15 / SCL0 / P2.14 SDA0 / P2.15 TEST VBIAS VSS VDD AIN0 / P3.0 AIN1 / P3.1 AIN2 / P3.2 AIN3 / P3.3 AIN4 / P3.4 AIN5 / P3.5 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 11/53 Block Diagram STR73xF 2.2.2 Table 2. Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 STR730F/STR735F (LFBGA144) STR730F/STR735F LFBGA ball connections Name P0.0 / OCMPB2 P6.10 / WUP8 P6.9 / TDO0 P6.12 / MOSI0 P6.6 / WUP6 V18 P5.15 / INT13 P5.8 / INT6 P5.2 / OCMPA9 P5.7 / MISO2 P5.6 / MOSI2 P5.11 / TDO2 / INT9 P0.8 / OCMPA6 P0.9 / OCMPB6 P0.10 / OCMPA7 P0.11 / OCMPB7 P0.12 / ICAPA3 P6.5 / WUP5 P6.0 / WUP0 P5.13 / INT11 P4.10 / ICAPA6 / WUP20 P4.9 / ICAPB6 P4.6 / SCL1 / WUP19 P4.5 / WUP18 / CAN2RX 1) P1.4 P1.11 / ICAPA0 / WUP29 P1.12 / ICAPA1 / WUP30 P2.7 / PWM5 VDD P2.9 / RDI1 / WUP14 Ball B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 Name P0.4 / OCMPA5 P0.1 / OCMPA2 P6.15 / WUP9 P6.13 / SCKO / WUP11 P6.7 / WUP7 P6.2 / WUP2 / RDI3 P5.14 / INT12 P5.9 / INT7 P5.3 / OCMPB9 P5.0 / MOSI1 P4.8 / OCMPA8 VDD P0.13 / ICAPB3 P0.14 / OCMPB3 P0.15 / OCMPA3 P1.0 / OCMPA4 P1.1 / OCMPB4 P6.1 / WUP1 P4.4 / CAN2TX1) P4.3 / ICAPB8 / WUP27 P4.2 / ICAPA8 / WUP26 P4.1 / ICAPB7 / WUP25 JTDI P1.6 / OCMPB1 P1.13 / ICAPB1 / WUP31 P2.1 / CAN1RX1) / WUP13 P2.6 / PWM4 M1 P2.8 / TDO1 P2.13 / INT15 P3.0 / AIN0 P3.4 / AIN4 VDDA VSSA P3.11 / AIN11 Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 Name P0.5 / OCMPB5 P0.2 / ICAPA2 P0.3 / ICAPB2 P6.14 / SSO P6.8 / RDI0 / WUP10 P6.3 / WUP3 VSS P5.10 / INT8 / RDI2 P5.4 / SS2 P5.1 / MISO1 P4.14 / SS1 P4.7 / SDA1 VSS P1.2 / ICAPB4 P1.3 / ICAPA4 VSS P1.5 P2.11 / WUP17 P4.0 / ICAPA7 / WUP24 VDD VSS JTDO JTCK nJTRST P1.7 / OCMPA1 P1.15 / CAN0TX1) P2.0 / PWM0 P2.3 / PWM1 RSTIN VSS P2.12 / INT14 VBIAS P3.3 / AIN3 P3.5 / AIN5 P3.7 / AIN7 P3.10 / AIN10 Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Name VSS VDD P0.6 / ICAPA5 P0.7 /ICAPB5 P6.11 / MISO0 P6.4 / WUP4 /TDO3 VDD P5.12 / INT10 P5.5 / SCK2 / WUP23 P4.13 / ICAPB9 P4.12 / ICAPA9 / WUP21 P4.11 / OCMPB8 VDD P1.8 / OCMPA0 / INT0 P1.9 / OCMPB0 / INT1 P1.10 / ICAPB0 / WUP28 XTAL2 P2.10 / WUP16 P2.15 / SDA 0 JTMS VSS VDD P3.15 / AIN15 / INT5 P3.14 / AIN14 / INT4 P1.14 / CAN0RX 1) / WUP12 P2.4 / PWM2 P2.5 / PWM3 P2.2 / CAN1TX1) M0 VSS XTAL1 TST P3.2 / AIN2 VSS VDD P3.6 / AIN6 B11 P4.15 / SCK1 / WUP22 C11 P2.14 / SCL 0 / WUP15 P3.1 / AIN1 P3.13 / AIN13 / INT3 P3.12 / AIN12 / INT2 P3.9 / AIN9 P3.8 / AIN8 Note 1: CAN alternate functions not available on STR735F. 12/53 STR73xF Block Diagram 2.2.3 STR731F/STR736F (TQFP100) Figure 4. STR731F/STR736F pin configuration (top view) P6.14 / SS0 P6.13 / SCK0 / WUP11 P6.12 / MOSI0 P6.11 / MISO0 P6.9 / TDO0 P6.8 / RDI0 / WUP10 P6.6 / WUP6 P6.4 / TDO3 / WUP4 P6.2 / RDI3 / WUP2 P6.0 / WUP0 VDD VSS V18 P5.12 / INT10 P5.11 / TDO2 / INT9 P5.10 / RDI2 / INT8 P5.9 / PWM5 / INT7 P5.8 / PWM4 / INT6 P5.7 / MISO2 P5.6 / MOSI2 P5.5 / SCK2 / WUP23 P5.4 / SS2 /PWM3 P5.1 / MISO1 P5.0 / MOSI1 P4.15 / SCK1 / WUP22 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 OCMPB2 / P0.0 OCMPA2 / P0.1 ICAPA2 / P0.2 ICAPB2 / P0.3 OCMPA5 / P0.4 OCMPB5 / P0.5 ICAPA5 / P0.6 VDD VSS ICAPA3 / P0.12 ICAPB3 / P0.13 OCMPB3 / P0.14 OCMPA3 / P0.15 OCMPA4 / P1.0 OCMPB4 / P1.1 ICAPB4 / P1.2 ICAPA4 / P1.3 OCMPB1 / P1.6 OCMPA1 / P1.7 INT0 / OCMPA0 / P1.8 INT1 / OCMPB0 / P1.9 ICAPB0 / WUP28 / P1.10 ICAPA0 / WUP29 / P1.11 ICAPA1 / WUP30 / P1.12 ICAPB1 / WUP31 / P1.13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 STR731F/STR736F 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P4.14 / SS1 P4.10 / ICAPB5 / WUP20 P4.7 / SDA1 P4.6 / SCL1 / WUP19 VDD VSS JTDO JTCK JTMS JTDI JTRST VSS VDD P3.15 / AIN11 / INT5 P3.14 / AIN10 / INT4 P3.13 / AIN9 / INT3 P3.12 / AIN8 / INT2 P3.11 / AIN7 P3.10 / AIN6 P3.9 / AIN5 P3.8 / AIN4 VDDA VSSA P3.7 / AIN3 P3.6 / AIN2 Note 1: CAN alternate functions not available on STR736F. WUP12 / CAN0RX / P1.14 CAN0TX / P1.15 PWM0 / P2.0 WUP13 / CAN1RX / P2.1 CAN1TX / P2.2 PWM1 / P2.3 PWM2 / P2.4 M0 RSTIN M1 VDD VSS XTAL1 XTAL2 VSS CAN2RX / TDO1 / P2.8 WUP14 / CAN2TX / RDI1 / P2.9 WUP15 / SCL0 / P2.14 SDA0 / P2.15 TEST VBIAS VSS VDD AIN0 / P3.4 AIN1 / P3.5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 13/53 Block Diagram Legend / Abbreviations for Table 3: Type: In/Output level: I = input, O = output, S = supply, HiZ= high impedance, STR73xF TT= TTL 0.8V / 2V with input trigger CT= CMOS 0.3VDD/0.7VDD with input trigger Port and control configuration: Input: pu/pd = with internal 100k weak pull-up or pull down OD = open drain (logic level) PP = push-pull Output: Interrupts: INTx =external interrupt line WUPx =Wake-Up interrupt line The reset state (during and just after the reset) of the I/O ports is input floating (Input Tristate TTL mode). To avoid excess power consumption, unused I/O ports must be tied to ground. Table 3. Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name STR73xF pin description Input interrupt pu/pd Output Capability Main functio n (after reset) OD Alternate function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A1 B2 C2 C3 D1 D2 B1 C1 D3 D4 E1 E2 E3 E4 F1 G1 E5 1 2 3 4 P0.0/OCMPB2 P0.1/OCMPA2 P0.2/ICAPA2 P0.3/ICAPB2 VSS VDD I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O TT TT TT TT 2mA X X Port 0.0 TIM2: Output Compare B output 2mA X X Port 0.1 TIM2: Output Compare A output 2mA X X Port 0.2 TIM2: Input Capture A input 2mA X X Port 0.3 TIM2: Input Capture B input Ground Supply voltage (5V) 5 6 7 P0.4/OCMPA5 P0.5/OCMPB5 P0.6/ICAPA5 P0.7/ICAPB5 P0.8/OCMPA6 P0.9/OCMPB6 TT TT TT TT TT TT TT TT 2mA X X Port 0.4 TIM5: Output Compare A output 2mA X X Port 0.5 TIM5: Output Compare B output 2mA X X Port 0.6 TIM5: Input Capture A input 2mA X X Port 0.7 TIM5: Input Capture B input 2mA X X Port 0.8 TIM6: Output Compare A output 2mA X X Port 0.9 TIM6: Output Compare B output 2mA X X 2mA X X Port 0.10 Port 0.11 TIM7: Output Compare A output TIM7: Output Compare B output P0.10/OCMPA7 I/O P0.11/OCMPB 7 8 9 VDD VSS I/O S S I/O PP Supply voltage (5V) Ground TT 2mA X X Port 0.12 TIM3: Input Capture A input 10 P0.12/ICAPA3 14/53 STR73xF Table 3. Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Block Diagram STR73xF pin description Input interrupt pu/pd Output Capability Main functio n (after reset) Port 0.13 Port 0.14 Port 0.15 OD Alternate function 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 F2 F3 F4 F5 F6 G2 G3 G4 H1 J1 G5 K1 L1 H2 H3 H4 J2 J3 K2 M1 L2 L3 K3 M4 L4 M2 11 P0.13/ICAPB3 12 P0.14/OCMPB 3 I/O I/O TT TT TT TT TT TT TT 2mA X X 2mA X X 2mA X X PP TIM3: Input Capture B input TIM3: Output Compare B output TIM3: Output Compare A output 13 P0.15/OCMPA3 I/O 14 P1.0/OCMPA4 15 P1.1/OCMPB4 16 P1.2/ICAPB4 17 P1.3/ICAPA4 VSS VDD P1.4 P1.5 18 P1.6/OCMPB1 19 P1.7/OCMPA1 20 P1.8/OCMPA0 21 P1.9/OCMPB0 22 P1.10/ICAPB0 23 P1.11/ICAPA0 24 P1.12/ICAPA1 25 P1.13/ICAPB1 I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 2mA X X Port 1.0 TIM4: Output Compare A output 2mA X X Port 1.1 TIM4: Output Compare B output 2mA X X Port 1.2 TIM4: Input Capture B input 2mA X X Port 1.3 TIM4: Input Capture A input Ground Supply voltage (5V) TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT INT0 INT1 2mA X X Port 1.4 2mA X X Port 1.5 2mA X X Port 1.6 TIM1: Output Compare B output 2mA X X Port 1.7 TIM1: Output Compare A output 2mA X X Port 1.8 TIM0: Output Compare A output 2mA X X Port 1.9 TIM0: Output Compare B output Port 1.10 Port 1.11 Port 1.12 Port 1.13 Port 1.14 Port 1.15 TIM0: Input Capture B input TIM0: Input Capture A input TIM1: Input Capture A input TIM1: Input Capture B input CAN0: Receive Data input CAN0: Transmit Data output WUP28 2mA X X WUP29 2mA X X WUP30 2mA X X WUP31 2mA X X WUP12 2mA X X 2mA X X 26 P1.14/CAN0RX I/O 27 P1.15/CAN0TX I/O 28 P2.0/PWM0 29 P2.1/CAN1RX 30 P2.2/CAN1TX 31 P2.3/PWM1 32 P2.4/PWM2 I/O I/O I/O I/O I/O 2mA X X Port 2.0 PWM0: PWM output WUP13 2mA X X Port 2.1 CAN1: Receive Data input 2mA X X Port 2.2 CAN1: Transmit Data output 2mA X X Port 2.3 PWM1: PWM output 2mA X X Port 2.4 PWM2: PWM output 15/53 Block Diagram Table 3. Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name STR73xF STR73xF pin description Input interrupt pu/pd Output Capability Main functio n (after reset) OD Alternate function 44 45 46 47 48 49 50 51 52 53 54 M3 K4 J4 M5 L5 K5 J5 M6 M7 H5 L6 P2.5/PWM3 P2.6/PWM4 P2.7/PWM5 33 M0 34 RSTIN 35 M1 36 VDD 37 VSS 38 XTAL1 39 XTAL2 40 VSS P2.8/TDO1/CA 41 N2RX I/O I/O I/O I I I S S I O S TT TT TT TT CT TT pd pu pd 2mA X X Port 2.5 PWM3: PWM output 2mA X X Port 2.6 PWM4: PWM output 2mA X X Port 2.7 PWM5: PWM output BOOT: Mode selection 0 input Reset input BOOT: Mode selection 1 input Supply voltage (5V) Ground Oscillator amplifier circuit input and internal clock generator input. Oscillator amplifier circuit output. Ground UART1: 2mA X X Port 2.8 Transmit Data output CAN2: Receive Data input (TQFP100 only) CAN2: Transmit Data output (TQFP100 only) 55 K6 I/O TT 56 J6 42 P2.9/RDI1/CAN I/O 2TX TT UART1: WUP14 2mA X X Port 2.9 Receive Data input Port 2.10 Port 2.11 Port 2.12 Port 2.13 Port 2.14 Port 2.15 I2C0:Serial Clock I2C0:Serial Data 57 58 59 60 61 62 63 H6 G6 L7 K7 J7 H7 M8 P2.10 P2.11 P2.12 P2.13 43 P2.14/SCL0 44 P2.15/SDA0 45 Test I/O I/O I/O I/O I/O I/O I TT TT TT TT TT TT pd WUP16 2mA X X WUP17 2mA X X INT14 INT15 2mA X X 2mA X X WUP15 2mA X X 2mA X X PP Reserved pin. Must be tied to ground 16/53 STR73xF Table 3. Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Block Diagram STR73xF pin description Input interrupt pu/pd Output Capability Main functio n (after reset) OD Alternate function PP 64 L8 46 VBIAS S Internal RC Oscillator bias. A 1.3M external resistor has to be connected to this pin when a 32kHZ RC oscillator frequency is used. Ground Supply voltage (5V) TT TT TT TT TT TT TT TT 2mA X X Port 3.0 ADC: Analog input 0 2mA X X Port 3.1 ADC: Analog input 1 2mA X X Port 3.2 ADC: Analog input 2 2mA X X Port 3.3 ADC: Analog input 3 2mA X X Port 3.4 2mA X X Port 3.5 2mA X X Port 3.6 2mA X X Port 3.7 ADC: Analog input 4 (AIN0 in TQFP100) ADC: Analog input 5 (AIN1 in TQFP100) ADC: Analog input 6 (AIN2 in TQFP100) ADC: Analog input 7 (AIN3 in TQFP100) 65 M10 47 VSS 66 M11 48 VDD 67 68 69 70 71 72 K8 J8 M9 L9 K9 P3.0/AIN0 P3.1/AIN1 P3.2/AIN2 P3.3/AIN3 49 P3.4/AIN4 S S I/O I/O I/O I/O I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O S TT TT TT TT TT TT TT TT INT2 INT3 INT4 INT5 L10 50 P3.5/AIN5 73 M12 51 P3.6/AIN6 74 75 76 77 78 79 80 81 82 83 84 85 L11 52 P3.7/AIN7 K11 53 VSSA K10 54 VDDA J12 J11 55 P3.8/AIN8 56 P3.9/AIN9 Reference ground for A/D converter Reference voltage for A/D converter 2mA X X Port 3.8 2mA X X Port 3.9 2mA X X 2mA X X 2mA X X 2mA X X 2mA X X 2mA X X Port 3.10 Port 3.11 Port 3.12 Port 3.13 Port 3.14 Port 3.15 ADC: Analog input 8 (AIN4 in TQFP100) ADC: Analog input 9 (AIN5 in TQFP100) ADC: Analog input 10 (AIN6 in TQFP100) ADC: Analog input 11 (AIN7 in TQFP100) ADC: Analog input 12 (AIN8 in TQFP100) ADC: Analog input 13 (AIN9 in TQFP100) ADC: Analog input 14 (AIN10 in TQFP100) ADC: Analog input 15 (AIN11 in TQFP100) L12 57 P3.10/AIN10 K12 58 P3.11/AIN11 J10 J9 59 P3.12/AIN12 60 P3.13/AIN13 H12 61 P3.14/AIN14 H11 62 P3.15/AIN15 H10 63 VDD Supply voltage (5V) 17/53 Block Diagram Table 3. Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name STR73xF STR73xF pin description Input interrupt pu/pd Output Capability Main functio n (after reset) Ground TT TT TT TT pu pu pu pd 4mA JTAG Reset Input JTAG Data input JTAG Mode Selection Input JTAG Clock Input JTAG data output. Note: Reset state = HiZ Ground Supply voltage (5V) TT TT TT TT TT TT TT TT TT TT WUP24 2mA X X Port 4.0 TIM7: Input Capture A input WUP25 2mA X X Port 4.1 TIM7: Input Capture B input WUP26 2mA X X Port 4.2 TIM8: Input Capture A input WUP27 2mA X X Port 4.3 TIM8: Input Capture B input 2mA X X Port 4.4 CAN2: Transmit Data output WUP18 2mA X X Port 4.5 CAN2: Receive Data input WUP19 2mA X X Port 4.6 I2C1:Serial Clock 2mA X X Port 4.7 I2C1:Serial Data 2mA X X Port 4.8 TIM8: Output Compare A output 2mA X X Port 4.9 TIM6: Input Capture B input TIM5: Input TIM6: Input Capture B Capture A input input (144-pin pkg (TQFP100 only) only) TIM8: Output Compare B output TIM9: Input Capture A input TIM9: Input Capture B input BSPI1: Slave Select BSPI1: Serial Clock OD Alternate function 86 87 88 89 90 91 92 93 94 95 96 97 98 99 H9 64 VSS S I I I I O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O G12 65 JTRST F12 66 JTDI H8 67 JTMS G11 68 JTCK G10 69 JTDO G9 G8 G7 F11 F10 F9 F8 E12 70 VSS 71 VDD P4.0/ICAPA7 P4.1/ICAPB7 P4.2/ICAPA8 P4.3/ICAPB8 P4.4/CAN2TX P4.5/CAN2RX 100 E11 72 P4.6/SCL1 101 C12 73 P4.7/SDA1 102 B12 103 E10 P4.8/OCMPA8 P4.9/ICAPB6 104 E9 74 P4.10/ICAPA6/I I/O CAPB5 PP TT WUP20 2mA X X Port 4.10 105 D12 106 D11 107 D10 P4.11/OCMPB 8 P4.12/ICAPA9 P4.13/ICAPB9 I/O I/O I/O I/O I/O TT TT TT TT TT 2mA X X WUP21 2mA X X 2mA X X 2mA X X WUP22 2mA X X Port 4.11 Port 4.12 Port 4.13 Port 4.14 Port 4.15 108 C11 75 P4.14/SS1 109 B11 76 P4.15/SCK1 18/53 STR73xF Table 3. Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Block Diagram STR73xF pin description Input interrupt pu/pd Output Capability Main functio n (after reset) OD Alternate function PP 110 B10 77 P5.0/MOSI1 111 C10 78 P5.1/MISO1 112 113 A9 B9 P5.2/OCMPA9 P5.3/OCMPB9 I/O I/O I/O I/O TT TT TT TT 2mA X X Port 5.0 2mA X X Port 5.1 BSPI1: Master Output/Slave input BSPI1: Master input/Slave output 2mA X X Port 5.2 TIM9: Output Compare A output 2mA X X Port 5.3 TIM9: Output Compare B output BSPI2: Slave 2mA X X Port 5.4 Select PWM3: PWM output (TQFP100 only) 114 C9 P5.4/SS2/PWM I/O 79 3 80 P5.5/SCK2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TT 115 D9 TT TT TT TT TT TT TT TT TT TT TT WUP23 2mA X X Port 5.5 BSPI2: Serial Clock 2mA X X Port 5.6 2mA X X Port 5.7 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 2mA X X Port 5.8 2mA X X Port 5.9 2mA X X 2mA X X 2mA X X 2mA X X 2mA X X 2mA X X Port 5.10 Port 5.11 Port 5.12 Port 5.13 Port 5.14 Port 5.15 1.8V decoupling pin: a decoupling capacitor (recommended value: 100nF) must be connected between this pin and nearest VSS pin. Ground Supply voltage (5V) BSPI2: Master Output/Slave input BSPI2: Master input/Slave output PWM4: PWM output (TQFP100 only) PWM5: PWM output (TQFP100 only) UART2: Receive Data input UART2: Transmit Data output 116 A11 81 P5.6/MOSI2 117 A10 82 P5.7/MISO2 118 119 120 A8 B8 C8 83 P5.8/PWM4 84 P5.9/PWM5 85 P5.10/RDI2 121 A12 86 P5.11/TDO2 122 123 124 125 D8 E8 B7 A7 87 P5.12 P5.13 P5.14 P5.15 126 A6 88 V18 S 127 128 C7 D7 89 VSS 90 VDD S S 19/53 Block Diagram Table 3. Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name STR73xF STR73xF pin description Input interrupt pu/pd Output Capability Main functio n (after reset) OD Alternate function 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 E7 F7 B6 C6 D6 E6 A5 B5 C5 A3 A2 D5 A4 B4 C4 B3 91 P6.0 P6.1 92 P6.2/RDI3 P6.3 93 P6.4/TDO3 P6.5 94 P6.6 P6.7 95 P6.8/RDI0 96 P6.9/TDO0 P6.10 97 P6.11/MISO0 98 P6.12/MOSI0 99 P6.13/SCK0 10 P6.14/SS0 0 P6.15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT WUP0 WUP1 WUP2 WUP3 WUP4 WUP5 WUP6 WUP7 8mA X X Port 6.0 2mA X X Port 6.1 2mA X X Port 6.2 UART3: Receive Data input 2mA X X Port 6.3 2mA X X Port 6.4 UART3: Transmit Data output 2mA X X Port 6.5 2mA X X Port 6.6 2mA X X Port 6.7 WUP10 2mA X X Port 6.8 UART0: Receive Data input 2mA X X Port 6.9 UART0: Transmit Data output WUP8 2mA X X 2mA X X 2mA X X WUP11 2mA X X 2mA X X WUP9 2mA X X Port 6.10 Port 6.11 Port 6.12 Port 6.13 Port 6.14 Port 6.15 BSPI0: Master input/Slave output BSPI0: Master Output/Slave input BSPI0: Serial Clock BSPI0: Slave Select 20/53 PP STR73xF Block Diagram 2.3 Memory Mapping Figure 5 shows the various memory configurations of the STR73xF system. The system memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure, the right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM addresses can be aliased to Block 0 addresses using the remapping feature Most reserved memory spaces (gray shaded areas in Figure 5) are protected from access by the user code. When an access this memory space is attempted, an ABORT signal is generated. Depending on the type of access, the ARM processor will enter "prefetch abort" state (Exception vector 0x0000_000C) or "data abort" state (Exception vector 0x0000_0010). It is up to the application software to manage these abort exceptions. Figure 5. 0xFFFF FFFF 0xFFFF 8000 Memory map APB Memory Space 32 Kbytes 0xFFFF FFFF 0xFFFF FC00 0xFFFF FBFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF F800 F7FF F600 F400 F3FF Addressable Memory Space 4 Gbytes APB TO ARM7 BRIDGE 32K EIC ADC CMU RTC DMA 0-3 TIM 4 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 7 0xE000 0000 0xDFFF FFFF FLASH Memory Space 64K/128/256 Kbytes 0x8010 DFFF 0xFFFF F000 0xFFFF EFFF 0xFFFF EC00 0xFFFF EBFF 6 0xC000 0000 0xBFFF FFFF 0x8010 C000 0x8010 0017 0x8010 0000 System Memory 8K Flash registers TIM 3 0xFFFF E800 0xFFFF E7FF 20B TIM 2 0xFFFF E400 0xFFFF E3FF 0xFFFF E000 0xFFFF DFFF 0xFFFF DC00 0xFFFF DBFF BSPI 2 BSPI 1 BSPI 0 GP I/O 0-6 PWM 0-5 CAN 2(4) CAN 1 (4) 5 0xA000 3FFF 0xA000 0000 0x9FFF FFFF RAM 0xFFFF D800 0xFFFF D7FF 0xFFFF D400 0xFFFF D3FF 16K 0xFFFF D000 0xFFFF CFFF 0xFFFF CC00 0xFFFF CBFF 4 0x8010 0017 0x8000 0000 0x7FFF FFFF FLASH 0xFFFF C800 0xFFFF C7FF 0xFFFF C400 0xFFFF C3FF CAN 0(4) APB BRIDGE 1 REGS reserved WAKEUP reserved TIM 5-9 TIM 1 TIM 0 WAKEUPTIM WDG UART 3 UART 1 UART 2 UART 0 TB 0-2 64K/128K/256K 0xFFFF C000 0xFFFF BFFF 0xFFFF BC00 0xFFFF BBFF 3 0x6000 03FF 0x6000 0000 0x5FFF FFFF PRCCU 0xFFFF B800 0xFFFF B7FF 0xFFFF B400 0xFFFF B3FF 1K 0x8003 FFFF 0xFFFF B000 0xFFFF AFFF B0F7(2) 64K 0xFFFF AC00 0xFFFF ABFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF A800 A7FF A600 A400 A3FF A200 A000 9FFF 9E00 9C00 9BFF 2 0x4000 003F 0x4000 0000 0x3FFF FFFF CONFIG. REGS 0x8003 0000 0x8002 FFFF 64B 0x8002 0000 0x8001 FFFF B0F6(2) 64K 1 0x2000 000F 0x2000 0000 0x1FFF FFFF NATIVE ARBITER B0F5(3) 64K 0xFFFF 9800 0xFFFF 97FF 0xFFFF 9400 0xFFFF 93FF reserved reserved reserved I2C 1 I2C 0 16B 0x8001 0000 0x8000 FFFF 0xFFFF 9000 0xFFFF 8FFF B0F4 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 8000 7FFF 6000 5FFF 4000 3FFF 2000 1FFF 0000 32K 8K 8K 8K 8K 0xFFFF 8C00 0xFFFF 8BFF 0xFFFF 8800 0xFFFF 87FF 0xFFFF 8400 0xFFFF 83FF 0xFFFF 8000 0 0x0010 0017 0x0000 0000 FLASH (1) B0F3 B0F2 B0F1 B0TF 64K/128K/256K APB BRIDGE 0 REGS (1) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes) (2) Only available in STR73xZ2/V2 (3) Only available in STR73xZ2/V2 and STR73xZ1/V1 (4) Only available in STR730/STR731 access to gray shaded area will return an ABORT Drawing not to scale 21/53 Electrical parameters STR73xF 3 3.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 3.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 3.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C and VDD=5V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 3.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 3.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 3.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 6. Pin loading conditions Figure 7. Pin input voltage STR7 PIN STR7 PIN L=50pF VIN 22/53 STR73xF Electrical parameters 3.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability Table 4. Symbol VDD - VSS VSSA VDDA- VSSA VIN |VDDx| |VSSX - VSS| VESD(HBM) VESD(MM) Voltage characteristics Ratings External 5V Supply voltage Reference ground for A/D converter Reference voltage for A/D converter Input voltage on any pin Variations between different 5V power pins Variations between all the different ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Min -0.3 VSS -0.3 -0.3 Max 6.0 VSS VDD+0.3 VDD+0.3 0.3 mV 0.3 Unit V V V see : Absolute Maximum Ratings (Electrical Sensitivity) on page 37 Table 5. Symbol IVDD IVSS IIO Current characteristics Ratings Total current into VDD power lines (source) 1) Total current out of VSS ground lines (sink) 1) Output current sunk by any I/O and control pin Output current source by any I/O and control pin Injected current on any other pin 4) &5) Total injected current (sum of all I/O and control pins) 4) Max. 100 100 10 mA 10 10 75 Unit IINJ(PIN) 2) & 3) IINJ(PIN) 2) 1. All 5V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 5V supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Electrical parameters Table 6. Thermal characteristics Ratings Storage temperature range Value -55 to +150 STR73xF Symbol TSTG TJ Unit C Maximum junction temperature (see Section 4.2: Thermal characteristics on page 49) 24/53 STR73xF Electrical parameters 3.3 Operating conditions Subject to general operating conditions for VDD, and TA. Table 7. Symbol fMCLK General Operating Conditions Parameter Internal CPU and system Clock frequency Standard Operating Voltage Operating Analog Reference Voltage with respect to ground Ambient temperature range 6 Partnumber Suffix 7 Partnumber Suffix Conditions Accessing SRAM or Flash (zero wait state Flash access up to 36 MHz) Min 0 Max 36 Unit MHz VDD 4.5 5.5 V VDDA TA 4.5 -40 -40 VDD+0.1 85 105 V C Table 8. Symbol tVDD Operating Conditions at power-up / power-down Parameter VDD rise time rate Conditions Subject to general operating conditions for TA. Min Typ 20 Max Unit - - ms/V 25/53 Electrical parameters STR73xF 3.3.1 Supply current characteristics The current consumption is measured as described in Figure 6 and Figure 7. Total current consumption The MCU is placed under the following conditions: All I/O pins in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for VDD, and TA. Table 9. Symbol Total Current consumption Parameter Conditions Formula, fMCLK in MHz, RAM execution RUN mode3) fMCLK=36 MHz, RAM execution fMCLK=36 MHz, Flash execution fOSC = 4 MHz, fMCLK= fOSC/16 = 250KHz Main Voltage Regulator ON, LP Voltage Regulator = 2mA, RTC and WDG ON, Other modules off. fRC = High Frequency (CMU_RCCTL= 0x8), fMCLK= fRC /16, LP Voltage Regulator = 2mA, Other modules off. fOSC = 4 MHz, RC oscillator ON fRC = High Frequency (CMU_RCCTL= 0x0) LP Voltage Regulator = 6mA, RTC and WUT ON, Other modules off. Internal wake-up possible. STOP mode fRC = High Frequency (CMU_RCCTL= 0xF), LP Voltage Regulator = 2mA. WUT ON. Other modules off. Internal wake-up possible. LP Voltage Regulator = 2mA, WIU ON, Other modules off, External wake-up. HALT mode LP Voltage Regulator = 2mA. Typ 1) 7 + 1.9 fMCLK 76 86 Max 2) Unit mA mA mA WFI mode 6.7 8 mA LPWFI mode IDD 220 350 A 500 700 A 150 220 50 50 140 140 A Notes: 1. Typical data are based on TA=25C, VDD=5V 2. Data based on characterization results, tested in production at VDD max. and TA = 25C. 3. I/O in static configuration (not toggling). RUN mode is almost independent of temperature. On the contrary RUN mode current is highly dependent on the application. The IDDRUN value can be significantly reduced by the application in the following ways: switch-off unused peripherals (default), reduce peripheral frequency through internal prescaler, fetch the most frequently-used functions from RAM and use low power mode when possible. 26/53 STR73xF Electrical parameters Figure 8. 300 250 200 STOP IDD vs. VDD Figure 9. 300 HALT IDD vs. VDD 250 Idd STOP (A) TA=-45C 150 100 50 0 3.5 4 4.5 5 Vdd (V) 5.5 6 6.5 TA=25C TA=85C TA=105C Idd HALT (A) 200 TA=-45C 150 TA=25C TA=85C TA=105C 100 50 0 3.5 4 4.5 5 Vdd (V) 5.5 6 6.5 Figure 10. WFI IDD vs. VDD 8.0 Figure 11. LPWFI IDD vs. VDD 500 7.5 450 400 Idd Wfi (mA) 7.0 TA=-45C TA=25C TA=85C Idd LPWFI (A) 350 300 250 200 150 100 50 0 TA=-45C TA=25C TA=85C TA=105C 6.5 TA=105C 6.0 5.5 3.5 4 4.5 5 Vdd (V) 5.5 6 6.5 3.5 4 4.5 5 Vdd (V) 5.5 6 6.5 27/53 Electrical parameters STR73xF Typical application current consumption Table 10. Typical consumption in Run mode at 25C and 85C Conditions Code executing in RAM fMCLK (MHz) fADC (MHz) Typical IDD (mA) 10 10 20 36 10 Code executing in Flash 10 20 36 9 32 48 9 29 42 22 VDD= 5.5 V, RC Oscillator off, PLL on, RTC enabled, 1 Timer (TIM) running, and ADC running in scan mode. 20 Table 11. Mode RUN Typical consumption in Run and low power modes at 25C Conditions All peripherals on, RAM execution 24MHz 56 mA 33 mA 31 mA 11 mA 8 mA 3 mA 2.5 mA 528 A 378 A 83 A 64 A 44 A 44 A Main Voltage Regulator on, Flash on, EIC on, WIU on, GPIOs on. PLL off, Main Voltage Regulator on CLOCK2/16, Main Voltage Regulator on, 36MHz 24MHz 4MHz 250kHz 250kHz 29kHz 250kHz fMCLK 36MHz Typical IDD 76 mA WFI SLOW CLOCK2/16, Main Voltage Regulator off, RC oscillator running in Low Frequency, Main crystal oscillator off, Main Voltage Regulator off LPWFI CLOCK2/16, Main Voltage Regulator off, LP Voltage Regulator = 2mA, Flash in power down mode. Main Voltage Regulator off, RTC on, RC oscillator off, LP Voltage Regulator = 6 mA Main Voltage Regulator off, RTC off, RC oscillator off, LP Voltage Regulator = 6 mA STOP Main Voltage Regulator off, RTC off, RC oscillator off, LP Voltage Regulator = 4 mA Main Voltage Regulator off, RTC off, RC oscillator off, LP Voltage Regulator = 2 mA HALT RTC off, LP Voltage Regulator = 2 mA 28/53 STR73xF Electrical parameters On-Chip Peripherals Table 12. Symbol IDD(RC) IDD(TIM) Peripheral current consumption at TA= 25C Parameter RC (Backup oscillator) supply current Low Frequency TIM Timer supply current 1) 60 350 1.1 850 430 5 2.88 2.95 fMCLK=36 MHz 150 250 240 370 2.5 180 570 300 460 A A mA A A mA mA mA A A A A mA A A A A Conditions High Frequency Typ 120 Unit A IDD(BSPI) BSPI supply current 1) IDD(UART) UART supply current 1) IDD(I2C) I2C supply current 1) IDD(ADC) ADC supply current when converting 2) IDD(EIC) EIC supply current IDD(CAN) CAN supply current 1) IDD(GPIO) GPIO supply current IDD(TB) TB supply current IDD(PWM) PWM supply current IDD(RTC) RTC supply current IDD(DMA) DMA supply current IDD(ARB) Native Arbiter supply current IDD(AHB) AHB Arbiter supply current IDD(WUT) WUT supply current IDD(WIU) Notes: WIU supply current 1. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset, not clocked and the on-chip peripheral when clocked and not kept under reset. This measurement does not include the pad toggling consumption. 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. 29/53 Electrical parameters STR73xF 3.3.2 Clock and timing characteristics Crystal / Ceramic Resonator Oscillator The STR73xF can operate with a crystal oscillator or resonator clock source. Figure 12 describes a simple model of the internal oscillator driver as well as example of connection for an oscillator or a resonator. Figure 12. Crystal Oscillator and Resonator STR73x VDD I RF XTAL1 XTAL2 STR73x XTAL1 XTAL2 XTAL1 STR73x XTAL2 Resonator Crystal RS CL CL Notes 1) XTAL2 must not be used to directly drive external circuits. 2) For test or boot purpose, XTAL2 can be used as an high impedance input pin to provide an external clock to the device. XTAL1 should be grounded, and XTAL2 connected to a wave signal generator providing a 0 to VDD signal. Directly driving XTAL2 may results in deteriorated jitter and duty cycle. 30/53 STR73xF VDD = 5V 10%, TA = -40C to TAmax, unless otherwise specified. Table 13. Symbol fOSC gm VOSC1) VAV1) Electrical parameters Main Oscillator characteristics Value Parameter Oscillator frequency Oscillator Transconductance Oscillation amplitude Oscillator operating point fOSC = 4 MHz, TA= 25oC fOSC = 8 MHz, TA= 25 C Sine wave middle, TA= 25oC External crystal, VDD = 5.5V, fOSC = 4 MHz, TA=-40oC External crystal, VDD = 5.0V, fOSC = 4 MHz, TA=25oC External crystal, VDD = 5.5V, fOSC = 6 MHz, TA=-40oC External crystal, VDD = 5.0V, fOSC = 6 MHz, TA=25oC External crystal, VDD = 5.5V, fOSC = 8 MHz, TA=-40oC External crystal, VDD = 5.0V, fOSC = 8 MHz, TA= 25oC o Conditions Min 4 1.5 2.4 1.0.77 5.5 3.3 2.7 12 8 7 Typ Max 8 4.2 - Unit MHz mA/V V V ms ms ms ms ms ms tSTUP1) Oscillator Start-up Time 31/53 Electrical parameters STR73xF Value Symbol Parameter Conditions Min C13) = C2 4)= 10pF fOSC = 4 MHz Cp2) = 10pF C1 = C2 = 20pF C1 = C2 = 30pF C1 = C2 = 40pF C1 = C2 = 10pF fOSC = 5 MHz Cp = 10pF C1 = C2 = 20pF C1 = C2 = 30pF C1 = C2 = 40pF C1 = C2 = 10pF RF1) Feedback resistor fOSC = 6 MHz Cp = 10pF C1 = C2 = 20pF C1 = C2 = 30pF C1 = C2 = 40pF C1 = C2 = 10pF fOSC = 7 MHz Cp = 10pF C1 = C2 = 20pF C1 = C2 = 30pF C1 = C2 = 40pF C1 = C2 = 10pF fOSC = 8MHz Cp = 10pF C1 = C2 = 20pF C1 = C2 = 30pF C1 = C2 = 40pF 150 490 490 380 160 415 340 260 160 325 250 180 160 260 185 135 155 210 145 100 Typ 555 1035 1030 850 470 800 735 580 415 640 550 420 375 525 420 315 340 435 335 245 Max Unit 1. Min and Max values are guaranteed by characterization, not tested in production. 2. CP represents the total capacitance between XTAL1 and XTAL2, including the shunt capacitance of the external quartz crystal as well as the total board parasitic cross-capacitance between XTAL1 track and XTAL2 track. 3. C1 represents the total capacitance between XTAL1 and ground, including the external capacitance tied to XTAL1 pin (CL) as well as the total parasitic capacitance between XTAL1 track and ground (this includes application board track capacitance to ground and device pin capacitance). 4. C2 represents the total capacitance between XTAL2 and ground, including the external capacitance tied to XTAL1 pin (CL) as well as the total parasitic capacitance between XTAL2 track and ground (this includes application board track capacitance to ground and device pin capacitance). 32/53 STR73xF Electrical parameters RC/Backup Oscillator characteristics VDD = 5V 10%, TA = -40C to TAmax, unless otherwise specified. Table 14. RC Oscillator Characteristics Symbol fRC fRCHF fRCLF Parameter RC Frequency RC High Frequency RC Low Frequency Conditions High Frequency mode 1) Low Frequency mode1) CMU_RCCTL = 0x0 CMU_RCCTL = 0xF CMU_RCCTL = 0x0 CMU_RCCTL = 0xF Fixed CMU_RCCTL Fixed CMU_RCCTL Stable VDD, fRC = 2.35 MHz, TA = 25oC Value Min Typ Max 2.35 29 3 2.3 35 30 10 23 2.35 Unit MHz kHz MHz MHz kHz kHz % % s fRCHFS2) RC High Frequency stability fRCLFS2) RC Low Frequency stability tRCSTUP RC Start-up Time 1) CMU_RCCTL = 0x8 2) RC frequency shift versus average value (%) PLL Electrical Characteristics VDD = 5V 10%, TA = -40C to TAmax, unless otherwise specified Table 15. Symbol PLL characteristics. Value Parameter Conditions Min Typ Max 3.0 5.0 20 x fPLLIN 12 x fPLLIN 28 x fPLLIN 16 x fPLLIN fPLLOUT/DX 120 240 240 480 100 300 1.5 36 MHz FREF_RANGE = `0' FREF_RANGE = `1' MX = "00" MX = "01" MX = "10" MX = "11" DX = 1..7 FREF_RANGE = `0', MX0 = '1' FREF_RANGE = `0', MX0 = '0' FREF_RANGE = `1', MX0 = '1' FREF_RANGE = `1', MX0 = '0' stable oscillator (fPLLIN = 4 MHz), stable VDD fPLLIN = 4 MHz (pulse generator) 1.5 3.0 Unit fPLLIN(1) PLL reference clock fPLLOUT PLL output clock MHz fMCLK (2) System clock PLL free running frequency MHz fFREE kHz tLOCK(3) tPKJIT PLL lock time PLL jitter (pk to pk) s ns 1. fPLLIN is obtained from fOSC directly or through an optional divider by 2. 2. Typical data are based on TA=25C, VDD=5V 3. Max value is guaranteed by characterization, not tested in production. 33/53 Electrical parameters Table 16. Symbol tWUHALT tWUSTOP STR73xF Low-power Mode Wake-up Timing Parameter Wake-up from HALT mode RC High Frequency in STOP mode Wake-up from STOP mode RC Low Frequency in STOP mode Main Voltage Regulator ON RC oscillator off fOSC = 4 MHz, fMCLK= fOSC/16 RAM or FLASH execution 27 s 234 s Conditions Typ 200 180 Unit s s tWULPWFI 1) Wake-up from LPWFI mode Main Voltage Regulator ON RC oscillator = High frequency FLASH execution Main Voltage Regulator ON RC oscillator = Low frequency FLASH execution 3.6 ms 46 s 1) FLASH memory has been programmed to enter Power Down mode during LPWFI. 34/53 STR73xF Electrical parameters 3.3.3 Memory characteristics Flash Memory Table 17. Symbol tWP tDWP tBP64 tBP128 tBP256 tSE8 tSE32 tSE64 tRPD3) tPSL3) tESL3) tESR3) Flash memory characteristics Value Parameter Word Program (32-bit) Double Word Program(64-bit) Bank Program (64K) Bank Program (128K) Bank Program (256K) Sector Erase (8K) Double Word Program Double Word Program Double Word Program Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed2) not preprogrammed preprogrammed 2) 2) Test Conditions Min Typ Max1) 35 64 0.5 1 2 0.6 0.5 1.1 0.8 1.7 1.3 80 150 1.25 2.5 4.9 0.9 0.8 2 1.8 3.7 3.3 20 10 30 Min time from Erase Resume to next Erase Suspend 20 20 Unit s s s s s s Sector Erase (32K) Sector Erase (64K) Recovery from Power-Down Program Suspend Latency Erase Suspend Latency Erase Suspend Rate s s s s s ms tSP3) tFPW3) NEND tRET Set Protection First Word Program Endurance Data Retention TA=85 10 20 40 1 170 s ms kcycles Years 1. TA=-45C after 0 cycles, Guaranteed by characterization, not tested in production 2. All bits programmed to 0. 3. Guaranteed by design, not tested in production. 35/53 Electrical parameters STR73xF 3.3.4 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 18. Symbol VFESD EMS data Parameter Conditions Level/ Class 4A Voltage limits to be applied on any I/O pin to VDD=5V, TA=+25C, fMCLK=36MHz induce a functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be VDD=5V, TA=+25C, fMCLK=36MHz applied through 100pF on VDD and VSS pins conforms to IEC 1000-4-4 to induce a functional disturbance VEFTB 4A 36/53 STR73xF Electrical parameters Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 19. EMI data Monitored Frequency Band 0.1MHz to 30MHz SEMI Peak level VDD=5.0V, TA=+25C, All packages 30MHz to 130MHz 130MHz to 1GHz SAE EMI Level Max vs. [fOSC4M/fMCLK] 6/36MHz 8/8MHz 23 37 20 4 30 34 7 3.5 dBV Unit Symbol Parameter Conditions Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. Table 20. Symbol VESD(HBM) VESD(MM) ESD Absolute Maximum ratings Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Electro-static discharge voltage (Charge Device Model) TA=+25C Conditions Maximum value 1) 2000 200 750 on corner pins, 500 on others Unit V VESD(CDM) Notes: 1. Data based on characterization results, not tested in production. Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each 37/53 Electrical parameters STR73xF sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical Sensitivities Symbol Parameter TA=+25C TA=+85C TA=+105C VDD=5.5V, fOSC4M=4MHz, fMCLK=32MHz, TA=+25C Conditions Class 1) A A A A LU DLU Notes: Static latch-up class Dynamic latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 38/53 STR73xF Electrical parameters 3.3.5 I/O port pin characteristics General Characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 21. Symbol VIL VIH IINJ(PIN) I/O static characteristics Parameter Input low level voltage 1) TTL ports Input high level voltage 1) Injected Current on any I/O pin 2.0 10 75 VSSVINVDD Floating input mode VIN=VSS VIN=VDD 55 55 200 120 120 5 220 220 1 mA mA A A k k pF Conditions Min Typ Max 0.8 V Unit IINJ(PIN) Total injected current (sum of all 2) I/O and control pins) Ilkg IS RPU RPD CIO Notes: 1. Data based on characterization results, not tested in production. Input leakage current 3) Static current consumption 4) Weak pull-up equivalent resistor5) Weak pull-down equivalent resistor5) I/O pin capacitance 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>V33 while a negative injection is induced by VIN Electrical parameters STR73xF Output Driving Current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 22. I/O Type Output driving current Symbol VOL 1) Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Conditions IIO=+2mA VDD-0.8 0.4 VDD-0.8 0.4 VDD-0.8 V Min Max 0.4 Unit Standard VOH 2) Med. Current (JTDO) High Current P6.0 Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin I =-2mA when 4 pins are sourced at same time IO Output low level voltage for an I/O pin IIO=+6mA VOL 1) VOH 2) Output high level voltage for an I/O pin IIO=-6mA Output low level voltage for an I/O pin IIO=+8mA VOL 1) VOH 2) Output high level voltage for an I/O pin IIO=-8mA Figure 13. VOH standard ports vs IOH @ VDD 5V Figure 14. VOL standard ports vs IOL @ VDD 5V TA -45c 5.10 0.25 5.00 0.20 Ta -45C Ta 25C Ta 90C Ta 110C VOH(V) at VDD= 5 V 4.90 VOL(V) at VDD= 5 V 2 3 4 0.15 4.80 4.70 Ta -45C Ta 25C Ta 90C Ta 110C 0.10 4.60 0.05 4.50 0 1 0.00 0 1 2 3 4 Ioh (mA) Iol (mA) 40/53 STR73xF Electrical parameters Figure 15. VOH JTDO pin vs IOL @ VDD 5V 5.10 Figure 16. VOL JTDO pin vs IOL @ VDD 5V 0.14 0.12 5.00 0.10 VOH(V) at VDD= 5 V 4.90 VOL(V) at VDD= 5 V 0.08 4.80 0.06 4.70 4.60 Ta -45C Ta 25C Ta 90C Ta 110C 0.04 0.02 Ta -45C Ta 25C Ta 90C Ta 110C 4.50 0 1 2 3 4 5 6 0.00 0 1.2 2.4 3.6 4.8 6 Ioh (mA) Iol (mA) Figure 17. VOH P6.0 pin vs IOL @ VDD 5V 5.10 Figure 18. VOL P6.0 pin vs IOL @ VDD 5V 0.18 0.16 5.00 0.14 VOH(V) at VDD= 5 V 4.90 VOL(V) at VDD= 5 V 0.12 0.10 0.08 0.06 0.04 0.02 0.00 4.80 4.70 4.60 Ta -45C Ta 25C Ta 90C Ta 110C Ta -45C Ta 25C Ta 90C Ta 110C 4.50 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Ioh (mA) Iol (mA) 41/53 Electrical parameters STR73xF NRSTIN Pin NRSTIN Pin Input Driver is CMOS. A permanent pull-up is present which is the same as RPU (see : General Characteristics on page 39) Subject to general operating conditions for VDD and TA unless otherwise specified. Table 23. Symbol VIL(NRSTIN) VIH(NRSTIN) Vhys(NRSTIN) VF(RSTINn) VNF(RSTINn) VRP(RSTINn) Notes: 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. Data guaranteed by design, not tested in production. Reset pin characteristics Parameter RSTIN Input low level voltage 1) RSTIN Input high level voltage 1) RSTIN Schmitt trigger voltage hysteresis 2) RSTIN Input filtered pulse3) RSTIN Input not filtered pulse3) RSTIN removal after Power-up3) 2 100 0.7 VDD 800 500 mV ns s s Conditions Min Typ 1) Max 0.3 VDD Unit V Figure 19. Recommended NRSTIN pin protection1) VDD RPU EXTERNAL RESET CIRCUIT 0.01F Filter INTERNAL RESET STR7X Required Notes: 1. The RPU pull-up equivalent resistor is based on a resistive transistor. 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRSTIN pin can go below the VIL(NRSTIN) max. level specified in Table 23. Otherwise the reset will not be taken into account internally. 42/53 STR73xF Figure 20. NRSTIN RPU vs. VDD 250 Electrical parameters 200 Rpu (kOhm) 150 25C -45C 110C 100 50 0 3 3.5 4 Vdd (v) 4.5 5 5.5 43/53 Electrical parameters STR73xF 3.3.6 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMCLK, and TA unless otherwise specified. Table 24. Symbol ADC characteristics Parameter Conditions Min 0.4 Conversion voltage range 2) VIN CADC tCAL2) tS3) 3.5 pF s 1/fADC s s 1/fADC mA A tCONV Total Conversion time (including sampling time) fADC = 10MHz 30 (10 for sampling +20 for successive approximation) 5 1 IADC Running mode Power-down mode Normal Mode Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDDA-VSS=5.0V. They are given only as design guidelines and are not tested. 2. Calibration is recommended once after each power-up. 3. During the sample time the input capacitance CAIN (6.8 max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. Table 25. Symbol |ET| |EO| |EG| |ED| |EL| ADC Accuracy with fMCLK = 20MHz, fADC=10MHz, RAIN < 10kRAIN, VDDA=5V. This assumes that the ADC is calibrated2) Parameter Total unadjusted error 1) Offset error 1) Gain Error 1) Differential linearity error1) Integral linearity error 1) Conditions Typ 1.0 0.15 0.97 0.7 0.76 Max 2.0 1.0 1.1 1.0 1.5 LSB Unit 1. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. The effect of negative injection current 44/53 STR73xF Electrical parameters on robust pins is specified in Section 3.3.5. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 3.3.5 does not affect the ADC accuracy. 2. Calibration is needed once after each power-up. Figure 21. ADC Accuracy Characteristics EG 1023 1022 1021 1LSB IDEAL V -V DDA SSA = ---------------------------------------(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 1024 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 5 6 7 1021 1022 1023 1024 VDDA V Figure 22. Typical Application with ADC VDD VT 0.6V RAIN VAIN CAIN VT 0.6V IL 1A AINx STR73X 2.3k(max) 10-Bit A/D Conversion CADC 3.5pF 45/53 Electrical parameters STR73xF Analog Power Supply and Reference Pins The VDDA and VSSA pins are the analog power supply of the A/D converter cell. They act as the high and low reference voltages for the conversion. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see: General PCB Design Guidelines). General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1F and optionally, if needed 10pF capacitors as close as possible to the STR7 power supply pins and a 1 to 10F capacitor close to the power source (see Figure 23). The analog and digital power supplies should be connected in a star network. Do not use a resistor, as VDDA is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs near the A/D input being converted. Software Filtering of Spurious Conversion Results For EMC performance reasons, it is recommended to filter A/D conversion outliers using software filtering techniques. Figure 23. Power Supply Filtering STR73x 1 to 10F STR7 DIGITAL NOISE FILTERING 0.1F VSS VDD 5V POWER SUPPLY SOURCE EXTERNAL NOISE FILTERING 0.1F VDDA VSSA 46/53 STR73xF Package characteristics 4 4.1 Package characteristics Package mechanical data Figure 24. 100-pin thin quad flat package D D1 A A2 Dim. A mm Min 0.05 1.35 0.17 0.09 16.00 14.00 16.00 14.00 0.50 0 0.45 3.5 0.60 1.00 100 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006 A1 A1 A2 b 1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.630 0.551 0.630 0.551 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008 b C D e E1 E D1 E E1 e L c L1 L h L1 N Number of Pins Figure 25. 144-pin thin quad flat package Dim. D D1 D3 A1 108 109 73 72 0.10mm .004 in. b Seating Plane E A A2 mm Min 0.05 1.35 0.17 0.09 1.40 0.22 Typ Max 1.60 0.15 0.002 1.45 0.053 0.27 0.007 0.20 0.004 Min inches Typ Max 0.063 0.006 0.057 0.011 0.008 A A1 A2 b c D D1 D3 E E1 c b E3 E1 21.80 22.00 22.20 0.858 0.867 0.874 19.80 20.00 20.20 0.780 0.787 0.795 17.50 0.699 21.80 22.00 22.20 0.858 0.867 0.874 19.80 20.00 20.20 0.780 0.787 0.795 17.50 0.50 0 0.45 3.5 0.60 1.00 144 7 0 0.699 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 144 1 e 37 36 E3 e K L1 L h L L1 N Number of Pins 47/53 Package characteristics Figure 26. 144-ball low profile fine pitch ball grid array package mm Min 1.21 0.21 1.085 0.35 0.40 8.80 8.80 0.80 0.60 0.10 0.15 0.08 Number of Pins N 144 Typ Max Min 0.008 1.70 0.048 STR73xF Dim. A A1 A2 b D D1 E E1 e F ddd eee fff inches Typ Max 0.067 0.043 0.45 0.014 0.016 0.018 0.346 0.346 0.031 0.024 0.004 0.006 0.003 9.85 10.00 10.15 0.388 0.394 0.400 9.85 10.00 10.15 0.388 0.394 0.400 Figure 27. Recommended PCB Design rules (0.80/0.75mm pitch BGA) 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print Dpad Dsm Dpad 48/53 STR73xF Package characteristics 4.2 Thermal characteristics The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) Where: - - - - - TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watt. This is the Chip Internal Power, PI/O represents the Power Dissipation on Input and Output Pins; User Determined. (1) Most of the time for the applications PI/O < PINT and may be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2 Where: - K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA Thermal Characteristics Description Package LFBGA144 JA Thermal Resistance Junction-Ambient TQFP144 TQFP100 Value (typical) 50 40 40 C/W Unit (2) (3) Table 26. Symbol 49/53 Order codes STR73xF 5 Table 27. Order codes Order Codes FLASH Kbytes 128 256 128 256 128 256 128 256 64 128 256 6 12 0 18 72 64 128 256 128 256 128 256 128 256 128 256 64 128 256 6 12 0 18 72 64 128 256 TQFP100 14x14 TQFP100 14x14 3 TQFP144 20x20 3 LFBGA144 10x10 10 16 32 112 TQFP144 20x20 0 LFBGA144 10x10 16 1 -40 to +105C TQFP100 14x14 TQFP100 14x14 3 Package TQFP144 20x20 3 LFBGA144 10x10 10 16 32 112 TQFP144 20x20 0 LFBGA144 10x10 16 1 -40 to +85C TIM 6x PWM CAN A/D Wake-up I/O RAM Lines Ports Kbytes Timers Module Periph Chan. Temp. Range Partnumber STR730FZ1T6 STR730FZ2T6 STR730FZ1H6 STR730FZ2H6 STR735FZ1T6 STR735FZ2T6 STR735FZ1H6 STR735FZ2H6 STR731FV0T6 STR731FV1T6 STR731FV2T6 STR736FV0T6 STR736FV1T6 STR736FV2T6 STR730FZ1T7 STR730FZ2T7 STR730FZ1H7 STR730FZ2H7 STR735FZ1T7 STR735FZ2T7 STR735FZ1H7 STR735FZ2H7 STR731FV0T7 STR731FV1T7 STR731FV2T7 STR736FV0T7 STR736FV1T7 STR736FV2T7 50/53 STR73xF Known limitations 6 6.1 Known limitations Low Power Wait For Interrupt mode When the STR73x device is put in Low Power Wait For Interrupt mode (LPWFI), the Flash goes into Low Power mode or Power Down mode, depending on the setting of the PWD bit in the Flash Control Register 0 (default is `0', Low Power mode). This default mode can create excessive voltage conditions on the transistor gates and may affect the long term behavior of the Low Power mode circuitry. Workaround There is no workaround. If Low Power Wait For Interrupt mode is used, it is strongly suggested to configure the Flash to enter Power Down mode (bit PWD = `1'). 6.2 PLL free running mode at high temperature When the STR73x device is operated and an ambient temperature (TA) of more than 55C and the main system clock (fMCLK) is sourced by the PLL in free running mode, the device may not work properly. Workaround At high temperature (more than 55C), it is recommended to use the internal RC oscillator as a backup clock source rather than the PLL free running mode. 51/53 Revision history STR73xF 7 Revision history Table 28. Date 19-Sep-2005 2-Nov-2005 Revision history Revision 1 2 First release Removed Table 8 power consumption in LP modes Updated PLL frequency in Section 1.1 and Table 12 Section 3.4: Preliminary power consumption data updated Section 3.5: DC electrical characteristics updated Section 6: Known limitations added. Section 3: Electrical parameters updated Section 6: Known limitations updated Added temperature range -40C to 85C in Section 5: Order codes Changed Flash data retention to 20 years at 85C in Table 17 on page 35. Changed Table 22: Output driving current on page 40 Added Figure 14: VOL standard ports vs IOL @ VDD 5V thru Figure 18: VOL P6.0 pin vs IOL @ VDD 5V on page 41. Added Figure 20: NRSTIN RPU vs. VDD Description of Changes 8-Mar-2006 3 4-Jun-2006 4 19-Jun-2006 5 08-Sep-2006 6 52/53 STR73xF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 53/53 |
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